An EE Times analysis has said a "sense of urgency" surrounds the semi conductor industry amid continued delays in developing new technology to produce the next generation of silicon chips.
Manufacturers of NAND flash are "leading the charge" in driving silicon scaling to ever smaller geometries but next generation lithography techniques were "dogged by delays" the engineering trade mag said.
The existing "immersion lithography" proceedure had been extended "far beyond what was once possible", wrote EE Times authors Dylan McGrath and Mark LaPedus. However the technique forced chipmakers to resort to "more and more expensive double-patterning steps."
The semiconductor manufacturing industry is pursuing several different next generation techniques, collectively called NGL for next-generation lithography. Extreme ultra-violet, maskless and nano-imprint are among the delayed technologies.
Despite the "sense of urgency" to find the viable technology solution, some of those being explored may never become commercially viable, including the leading EUV process.
The lack of a viable NGL raises the spectre of a crunch period at which point the existing process cannot be shrunk further while no new process yet exists to deliver the smaller, faster chips of tomorrow.
Image: Intel 45nm silicon wafer.